Resources

Semiconductor workforce glossary

The terms you will meet on a semiconductor line and in India's workforce programmes, explained plainly.

Advanced packaging: Packaging methods beyond traditional wire bond, such as flip-chip, fan-out, 2.5D and 3D integration, that place chips closer together for better performance. Hire by role
ATE (Automated Test Equipment): Machines that electrically test chips against their specification, run by test programs written by test engineers.
ATMP: Assembly, Testing, Marking and Packaging. The back-end stage where finished wafers become packaged, tested chips. Often used alongside OSAT in India's policy language.
Back end: The manufacturing steps after wafer fabrication: assembly, packaging and test.
Cleanroom: A controlled environment where airborne particles, temperature and humidity are kept within strict limits so they do not damage wafers or chips.
CMP (Chemical Mechanical Planarisation): A fab process that polishes wafer surfaces flat between layers using chemical slurry and mechanical pads.
Delivery partner: An institution that runs Nirji workforce programmes on its campus using the Academy-in-a-Box model. Become a Delivery Partner
Die attach: The assembly step that fixes a chip (die) onto its substrate or lead frame using adhesive, solder or sintering.
Deployment outcomes: How candidates perform once placed on a line. Nirji checks performance at 30 and 90 days after deployment.
EHS: Environment, Health and Safety. The systems and roles that keep people, plant and environment safe in semiconductor manufacturing.
Etch: A fab process that removes material from the wafer in a defined pattern, using plasma (dry) or chemicals (wet).
Fab: A wafer fabrication plant, where circuits are built layer by layer on silicon wafers.
Failure analysis: The investigation of why a chip or package failed, using electrical, optical and physical techniques.
Flip-chip: A packaging method where the chip is turned face down and connected to the substrate through bumps instead of wires.
Front end: Wafer fabrication: the steps that build circuits on the wafer, before assembly and test.
Metrology: Measurement of wafer and process characteristics, such as film thickness and feature size, to keep processes in control.
Mould (encapsulation): The assembly step that encloses the chip and its connections in protective compound.
Nirji Ready certification: Nirji Semicon's assessment that a candidate meets the competency level required for a specific role on the line. About Nirji Ready
OSAT: Outsourced Semiconductor Assembly and Test. Companies that package and test chips on behalf of chip makers.
Photolithography: The fab process that transfers circuit patterns onto the wafer using light and photoresist.
Preventive maintenance (PM): Scheduled servicing of equipment to prevent breakdowns and keep tools within specification.
Reliability qualification: Stress testing, such as temperature cycling and humidity tests, that shows a product will last in the field.
Semicon 2.0: The second phase of the India Semiconductor Mission, extending support across chip design, equipment and materials, fabs, advanced packaging and R&D. Read the Semicon 2.0 Guide
SPC (Statistical Process Control): Using charts and statistics to monitor a process and act before it drifts out of specification.
Talent Cloud: Nirji's registry of assessed semiconductor candidates, matched to roles and workforce programmes. Join the Talent Cloud
Thin film (CVD / PVD): Fab processes that deposit very thin layers of material onto the wafer by chemical (CVD) or physical (PVD) vapour deposition.
UPW (Ultra-pure water): Water purified far beyond drinking standards, used in large volumes to rinse wafers in fabs.
Wire bond: An assembly method that connects the chip to its package with very fine metal wires.
Workforce Architecture: Nirji's framework that maps each role to competencies at four levels, from L1 (supervised) to L4 (expert and coaching). About Workforce Architecture
Workforce programme: A client-defined programme that prepares candidates for specific semiconductor roles, delivered with partner institutions. Browse workforce programmes
Yield: The share of chips that meet specification out of all produced. Improving yield is a core job for process and yield engineers.

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